Today, functional verification consumes most of the time in the design of layered protocols like OSI Model, PCI Express, etc. As we think of reuse of design components, the reuse of verification ...

The need to improve functional verification productivity and quality continues to grow. The 2004/2002 IC/ASIC Functional Verification Study, by Collett International Research, shows that logic or ...

The SoC industry needs a reuse-oriented, coverage-driven verification methodology built on the rich semantic support of a standard language. This is the second in a series of four articles outlining a ...

The electronics industry is constantly challenged by the ever-growing design and verification requirements for complex chips. With the IEEE-Std 1800-2005 System-Verilog standard, the industry has a ...

Mixed signal IP design and verification have become increasingly complex and compute-intensive. It is important to detect any functional or, in worst case, architectural bugs early in the design cycle ...

Standard cell libraries have been a mainstay of chip design for many decades since the inception of logic synthesis and composition methodologies. Cell library IP typically contains Verilog models ...

There’s an old saying about simulation: “It’s all about the need for speed.” Simulation is the core technology for functional verification of semiconductors, and the demand for higher runtime ...

More processors on SoCs means more sophisticated cache control. This article describes formal techniques for verifying cache coherency for the ARM AMBA AXI Coherency Extensions (ACE) protocol. Fig 1.